1. Field of the Invention
The present invention relates to a Mask read-only memory(Mask ROM), and particularly to a Via Code Mask ROM having a smaller circuit area.
2. Description of the Prior Art
Mask ROM is a basic kind of ROM. In manufacturing of a Mask ROM, the connections within the array of the memory cells for storing particular information are determined by a mask. Thus, to manufacture a ROM for storing different information, only the mask need be modified rather than the whole process of manufacture the ROM.
Referring to FIG. 1, a traditional Mask ROM comprises a row address decoder 101 receiving a row address 104, a column address decoder 102 receiving a column address 105 and having an output 106, and an array 103 of memory cells. The array 103 of memory cells comprises an array of transistors 111xcx9c144, 4 bit lines C1xcx9cC4 connected to the column address decoder 102 and 4 word lines R1xcx9cR4 connected to the row address decoder 101. In the array of the transistors 111xcx9c144, the connections between the transistors 111xcx9c144 and the bit lines C1xcx9cC4 are carried out by Via Code and shown in FIG. 1, wherein a black dot on the intersection of two crossed lines represents an electrical connection.
The operation of the traditional Mask ROM in FIG. 1 will be explained below. Initially, given that the voltage level on each of the word lines R1xcx9cR4 is lower than the threshold voltage, all the transistors 111xcx9c144 are turned off and the voltage level on each of the bit lines C1xcx9cC4 represents a xe2x80x9c1xe2x80x9d (logic high). When receiving the row address 104, the row address decoder 101 pulls up the voltage level on one of the word lines R1xcx9cR4 accordingly, to turn on a corresponding row of transistors. Specifically, if the word line R1 is selected, the voltage level thereon is pulled up to be higher than the threshold voltage and the transistors 111xcx9c114 are turned on. Since the bit lines C1, C3 and C4 are connected to the drains/sources of the transistor 111, 113 and 114, the logic levels of bit lines C1, C2, C3 and C4 are 0, 1, 0 and 0, respectively, when the word line R1 is selected. If the word line R2 is selected, the voltage level thereon is pulled up to be higher than the threshold voltage and the transistors 121xcx9c124 are turned on. Since the bit lines C1 and C3 are connected to the drains/sources of the transistor 121 and 123, the logic levels of bit lines C1, C2, C3 and C4 are 0, 1, 0 and 1, respectively, when the word line R2 is selected. If the word line R3 is selected, the voltage level thereon is pulled up to be higher than the threshold voltage and the transistors 131xcx9c134 are turned on. Since the bit lines C2 and C4 are connected to the drains/sources of the transistor 132 and 134, the logic levels of bit lines C1, C2, C3 and C4 are 1, 0, 1 and 0, respectively, when the word line R3 is selected. If the word line R4 is selected, the voltage level thereon is pulled up to be higher than the threshold voltage and the transistors 141xcx9c144 are turned on. Since the bit lines C1, C2, C3 and C4 are connected to the drains/sources of the transistor 141, 142, 143 and 144, the logic levels of bit lines C1, C2, C3 and C4 are 0, 0, 0 and 0, respectively, when the word line R4 is selected.
Afterwards, the column address decoder 101 receives the column address 105 and accordingly selects a voltage level from one of the bit lines C1xcx9cC4 as the output 106. Therefore, the output 106 can be a value selected from the 16 values (0, 1, 0, 0), (0, 1, 0, 1), (1, 0, 1, 0), (0, 0, 0, 0) according to the row and column address 104 and 105. That is to say, the Mask ROM in FIG. 1 is a 16-bit ROM.
Generally, there are two kinds of code used to carry out the connections between the transistors and the bit lines. They are Buried P+ Code and Via Code. In a Buried P+ Code Mask ROM, the Buried P+ Code is under the gate of a transistor so that it is possible for two adjacent transistors to have a common drain/source. However, in a Via Code Mask ROM, the Via Code is under the drain/source of a transistor so that a common drain/source for two adjacent transistors is not practicable. Thus makes the required circuit area for the Via Code Mask ROM larger than that for the Buried P+ Code Mask ROM.
In order to solve the above problem, it is therefore one object of the invention to provide a Via Code Mask ROM with a smaller circuit area.
The present invention provides a Via Code Mask read-only memory comprising an array of transistors, and a plurality of bit lines and word lines, wherein the transistors in each row of the array are connected in series by connection of a drain/source of one transistor with a drain/source of another transistor. Both ends of the series of the transistors in each row of the array are connected to a supply voltage together. Each one of the bit lines is selectively connected to drain(s)/source(s) of one or more transistors in one corresponding column. Each one of the word lines connects together gates of the transistors in one corresponding row.
Accordingly, in the present invention, most of the transistors are placed at the spaces between two adjacent bit lines. People skilled in the art will appreciate that there is sufficient space between two adjacent bit lines. Thus, there is no need for an additional circuit area for the transistors, which makes the whole circuit area of a Via Code Mask ROM smaller.